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International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289)
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IJTEEE >> Volume 3 - Issue 11, November 2015 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



Low Voltage Low Power Applications Of 3T Gain Cell

[Full Text]

 

AUTHOR(S)

Padma Priya. M, Sasikala.P

 

KEYWORDS

Index Terms: Access speed, data retention time, embeddedDRAM, gain cell, low power operation.

 

ABSTRACT

Abstract: Logic compatible gain cell (GC)-embedded DRAM (eDRAM) arrays are considered an alternative to SRAM due to their small size, nonratioed operation, low static leakage, and two-port functionality. However, traditional GC-eDRAM implementations require boosted control signals in order to write full voltage levels to the cell to reduce the refresh rate and shorten access times. These boosted levels require either an extra power supply or on-chip charge pumps, as well as nontrivial level shifting and toleration of high voltage levels. In this brief, we present a novel, logic compatible, 3T GC-eDRAM bitcell that operates with a single-supply voltage and provides superior write capability to the conventional GC structures. The proposed circuit is demonstrated with a 2-kb memory macro that was designed and fabricated in a mature 0.18-µm CMOS process, targeted at low-power, energy-efficient applica-tions. The test array is powered with a single supply of 900 mV, showing a 0.8-ms worst case retention time, a 1.3-ns write-access time, and a 2.4-pW/bit retention power. The proposed topology provides a bitcell area reduction of 43%, as compared with a redrawn 6-transistor SRAM in the same technology, and an overall macro area reduction of 67%including peripherals.

 

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