Survey On Various Works Done In Reducing Static Power In Various SRAM Cells
Deepti Kanoujia, Vishal Moyal
Keywords: CMOS, Chip density, Parasitic capacitance, Scaling, 5T SRAM Cell, Power dissipation, Power reduction.
ABSTRACT: Memory is the basic need of most of the electronic devices. These memories are mainly designed using CMOS transistors. As we talk about CMOS transistors power, area and speed of each transistor is a major issue of concern. But we know that there is a trade-off between these three factors. Still engineers and researchers are working upon these issues. Issue arises when we switch to lower technologies as within the same die area we have to implant more number of transistors which leads to high chip density and thus high parasitic capacitance. Scaling of transistors is another factor. Thus in this paper we will study about various works done in reducing power dissipation in 5T SRAM cell using different methods in different technologies, a bit compromising in area and speed.
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