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IJTEEE >> Volume 1 - Issue 4, November 2013 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



High Speed Viterbi Decoder Design With A Rate Of 1/2 Convolution Code For Tcm Systems

[Full Text]

 

AUTHOR(S)

Anam Srinivasa Reddy, P. Rama Krishna

 

KEYWORDS

Key words: Viterbi decoder, convolution encoder, TCM, T-algorithm, FPGA.

 

ABSTRACT

High speed Viterbi decoder design for trellis coded modulation (TCM) is presented in this paper. It is well known that the Viterbi decoder (VD) is the dominant module for determining shortest path. We propose a pre-computation architecture incorporated with T-algorithm for VD, which can find the shortest path without degrading the decoding speed much. A general solution to derive the optimal pre-computation steps is also given in the paper. Implementation result of a VD for a rate-1/2 convolution code used in a TCM system shows that compared with the full trellis VD, with the constraint length 9. This work focuses on the realization of convolution encoder and adaptive Viterbi decoder (AVD) with a constraint length (K) of 9 and a code rate (k/n) of 1/2, Implemented on FPGA. The results are tested by using ISE 10.1 and Modelsim.

 

REFERENCES

[1]. J. He, H. Liu, and Z. Wang, “A fast ACSU architecture for Viterbi decoder using T-algorithm,” in Proc. 43rd IEEE Asilomar Conf. Signals, Syst. Comput., Nov. 2009, pp. 231–235.

[2]. J. He, Z. Wang, and H. Liu, “An efficient 4-D 8PSK TCM decoder architecture,” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., vol. 18, no. 5, pp. 808–817, May 2010.

[3]. J. Jin and C.-Y. Tsui, “Low-power limited-search parallel state viterbi decoder implementation based on scarece state transition,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 11, pp. 1172–1176, Oct. 2007.

[4]. J. He, H. Liu, Z. Wang,X.Huang and Kai Zhang ,“High-Speed Low-Power Viterbi Decoder Design for TCM Decoders” in IEEE Trans.on (VLSI) Systems, Vol. 20, No. 4, April 2012.

[5]. High-Speed Low-Power Viterbi Decoder Design for TCM Decoders Jinjin He,Huaping Liu, Zhongfeng Wang, Xinming Huang, and Kai Zhang IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 15, no. 11, pp. 1172– 1176 January 19, 2011.

[6]. J. B. Anderson and E. Offer, “Reduced-state sequence detection with convolutional codes,” IEEE Trans. Inf. Theory, vol. 40,no. 3,pp. 965-972,May 2008.

[7]. C. F. Lin and J. B. Anderson, “M-algorithm decoding of channel convolutional codes”, presented at the Princeton Conf. Info. Sci. Syst., Princeton, NJ, Mar. 2006.

[8]. F. Chan and D. Haccoun, “Adaptive Viterbi decoding of convolutional codes over memory less channels”, IEEE Trans. Commun., vol. 45,no. 11,pp. 1386-1400,Nov2006.

[9]. S. J. Simmons, “Breadth-first trellis decoding with adaptive effort”, IEEE Trans. Commun., vol. 38, no. 1,pp. 3-12, Jan.2004.[6]Bandwidth-efficient modulations, Consultive Committee For Space Data System, Matera, Italy, CCSDS 401(3.3.6)Green Book, Issue 1,Apr. 2003.