A Low Power And Reliable 12T SRAM Cell Considering Process Variation In 16nm CMOS
[Full Text]
AUTHOR(S)
Mohsen Imani, Haleh Alimohamadi
KEYWORDS
Keywords: SRAM Cell, SNM, Reliability, Process variation
ABSTRACT
ABSTRACT: In this paper a new 12TSRAM cell employing 16nm CMOS technology is introduced. The cell has separate read and write paths. For reducing the power consumption, this cell inserts a transistor for isolating the supply voltage rail from cell. This transistor acts as a power gating transistor in hold mode and feedback in active mode. Also this transistor with weakening the cell in active mode, improves the write access time and write margin. The read path of proposed cell buffers by two transistors which reduces its leakage current corresponds to the stacking effect. This cell deforms the butterfly diagram and increases the available SNM. In comparison of proposed cell with 9T SRAM and Schmitt trigger 10T (SC10T) structures shows that proposed cell has 75.5% and 4.6% higher read SNM and 25% and 20% lower write access time respect to 9TCell and ST10T cells respectively. The hold power of proposed cell is also 4.24X and 4.17X lower than the other cells.
REFERENCES
[1] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, "Lowpower CMOS digital design," IEICE Transactions on Electronics, vol. 75, pp. 371382, 1992.
[2] M. Jafari, M. Imani, and M. Fathipour, "A 13 ENOB and 40MS/s SwitchedCapacitor Sample & Hold Circuit Using a TwoStage OTA with nonideal components available in CMOS 0.18 µ technology."
[3] M. Muker and M. Shams, "Designing digital subthreshold CMOS circuits using parallel transistor stacks," Electronics letters, vol. 47, pp. 372374, 2011.
[4] H. M. Vo, C.M. Jung, E.S. Lee, and K.S. Min, "Dualswitch power gating revisited for small sleep energy loss and fast wakeup time in sub45nm nodes," IEICE Electronics Express, vol. 8, pp. 232238, 2011.
[5] H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy, "Ultra lowpower clocking scheme using energy recovery and clock gating," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17, pp. 3344, 2009.
[6] S. Dighe, S. Vangal, P. Aseron, S. Kumar, T. Jacob, K. Bowman, et al., "Withindie variationaware dynamicvoltagefrequency scaling core mapping and thread hopping for an 80core processor," in SolidState Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, 2010, pp. 174175.
[7] W.B. Yang, C.H. Wang, I. Chuo, and H.H. Hsu, "A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralowpower application," in Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on, 2012, pp. 604608.
[8] A. Islam and M. Hasan, "Variability aware low leakage reliable SRAM cell design technique," Microelectronics reliability, vol. 52, pp. 12471252, 2012.
[9] G. Chen, D. Sylvester, D. Blaauw, and T. Mudge, "Yielddriven nearthreshold SRAM design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 18, pp. 15901598, 2010.
[10] M. Ansari, M. Imani, H. Aghababa, and B. Forouzandeh, "Estimation of joint probability density function of delay and leakage power with variable skewness," in Electronics, Computer and Computation (ICECCO), 2013 International Conference on, 2013, pp. 251254.
[11] Z. Liu and V. Kursun, "Characterization of a novel ninetransistor SRAM cell," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, pp. 488492, 2008.
[12] J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV robust schmitt trigger based subthreshold SRAM," SolidState Circuits, IEEE Journal of, vol. 42, pp. 23032313, 2007.
[13] A. Agarwal, H. Li, and K. Roy, "DRGcache: a data retention gatedground cache for low power," in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 473478.
