A Low Power And Reliable 12T SRAM Cell Considering Process Variation In 16nm CMOS
Mohsen Imani, Haleh Alimohamadi
Keywords: SRAM Cell, SNM, Reliability, Process variation
ABSTRACT: In this paper a new 12T-SRAM cell employing 16nm CMOS technology is introduced. The cell has separate read and write paths. For reducing the power consumption, this cell inserts a transistor for isolating the supply voltage rail from cell. This transistor acts as a power gating transistor in hold mode and feedback in active mode. Also this transistor with weakening the cell in active mode, improves the write access time and write margin. The read path of proposed cell buffers by two transistors which reduces its leakage current corresponds to the stacking effect. This cell deforms the butterfly diagram and increases the available SNM. In comparison of proposed cell with 9T SRAM and Schmitt trigger 10T (SC10T) structures shows that proposed cell has 75.5% and 4.6% higher read SNM and 25% and 20% lower write access time respect to 9TCell and ST10T cells respectively. The hold power of proposed cell is also 4.24X and 4.17X lower than the other cells.
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