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International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289)
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IJTEEE >> Volume 3 - Issue 4, April 2015 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



A Review On Design And Analysis Of D Flip Flop With Different Technologies

[Full Text]

 

AUTHOR(S)

Hardeep Kaur, Sukhdeep Kaur, Er. Poonam Rani

 

KEYWORDS

Keywords: Flip flop,CMOS,GDI,DETFF ,CNTFET, Power disipation

 

ABSTRACT

Abstract: The Field of Digital Electronics have been directly towards to the low power of digital system. Recently the requirement of Probability and the improvement in battery performance indicate power dissipation is one of the most critical design parameter. wide utilization of memory storage systems and sequential logic in modern electronics triggers a demand for high performance and low area implementations of basic memory component one of the most state holding element is D flip flop. Here the proposed work is to design and analyze the D flip flop using CMOS, GDI technique, DETFF and CNTFET techniques and then compared with each other for power dissipation. The whole process of design and analysis of D flip flop and simulation will be done by using Tanner EDA.

 

REFERENCES

[1] Vladimir Stojanovic and vojin G.oklobdizia,Fellow IEEE, Comparative Analysis of Master Slave latches and flip flops for high performance and low system ,IEEE journal of solid state circuits ,vol.34,No.4 April 1999

[2] Arkadiy Morgenshtein, Alexander Fish and Israel A,Wagner, Gate Diffusion Input- A power efficient method for digital combinational circuits, IEEE Transactions very large scale integration(VLSI) systems,vol.10,No. 5 October 2002

[3] Kuo-Hsing Cheng and Yung- Hsinang Lin, A dual pulse clock double edge triggered flip flop for low voltage and high speed applications,IEEE,2003

[4] Arkadiy Morgenshtein, Alexander Fish and Israel A,Wagner, An efficient implementation of D flip flop using GDI Technique, IEEE 2004

[5] M.W.phyu,W. L Goh and K.S Yeo, A low power Static dual Edge triggered Flip flop using an output controlled Discharge configuration, IEEE 2005

[6] Fatemeh Aezinia,Sara Najafzadeh and Ali Afzali-kusha, Novel high speed and low power single and double edge triggered flip flops,IEEE 2006

[7] Yu Chien- Cheng, Design low poer double edge triggered flip flop circuit, IEEE 2007

[8] Manoj Sharama, Dr. Aarti noor, shatish Chandara Tiwari, Kunwar singh, International conference on Advances in recent Technologies in computation and computing ,IEEE 2009

[9] Jin-fa Lin, Ming-Hwa Sheu and Peng-siang Wang, A low power dual mode pulse Triggered flip flop using Pass transistor logic, IEEE 2010

[10] Wing –shan Tam, Sik-Lam siu,Chi wah kok and Hei wong, International conference of Electron Devices and solid state circuits, IEEE 2010

[11] K.G Sharama ,Tripti Sharama , B.P singh and Manisha sharama, Modified Set D flip flop Design for Low power Vlsi applications.IEEE 2011

[12] Sayed E.eamaili, Asim j, Al-Kahili, and Gleen E.R cowan, Low swing Differential conditional capturing flip flop for LC resonant circuit,IEEE 2011

[13] Panshul Dobriyal, Karna sharama,Manan Sethi ,Geetanjli Sharma, A high performance D flip flop Design with low power clocking system using MTCMOS Technique, IEEE 2012

[14] Y.syamala, K.Srilakshmi and someshkar varma, Design of Low power CMOS logic circuits using Gate Diffusion Technique,international Jouranal of VLSI design & communication systems (VLSICS) ,vol. 4,No. 5,October 2013,

[15] N.Vishnu Vardhan Reddy, C.Leela mohan & M.srilakshami, GDI based subthreshold low power D flip flop,International jouranal of VLSI and Embedded system,2013

[16] M.Guru Santhana Bharathi ,P.Nagarajan, Design of storage element for low power VLSI system,IJISET,2014

[17] Amit Grover , Sumer singh, D flip flop with different Technologies, Advanced engineering technology and application,2014

[18] Priya Jose, An optimal Flip flop design for VLSI power minimization, IJAET 2014

[19] A.vinodhini, S.susikala, T.N priyatharshne, An optimized Fault Analysis using Dual Logic IJARCSSE 2014

[20] Jin –Fa Lin, Low power pulse triggered Flip flop design based on a signal feed Through Scheme, IEEE Transactions on very Large scale integration (VLSI) systems ,Vol.22,No.1.Januarary 2014

[21] R.dhivya bharathi ,M.sunil karthik, A pass transistor based D flip flop design using negative edge triggered circuit, IJERST 2015