Low Power Sram Design Using MultiBit FlipFlop (MBFF)
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AUTHOR(S)
Lincy J, Sivasankar Rajamani P
KEYWORDS
Keywords: low power, clock power, merging, multibit flipflop, time violation.
ABSTRACT
ABSTRACT: The increasing demand for batterypowered and greencompliant applications has made power management a dominant factor in SoC design. Clock power contributes 40% of total chip power.To get maximum reduction in power an algorithm has been proposed in which singlebit flipflops are replaced with maximum possible MultiBit FlipFlop (MBFF) without affecting the performance of the original circuit. Firstly mergable flipflops are identified based on synchronous clocking and replaced without affecting the performance however replacement will change the location of flipflops leading to timing and capacity constraint. Tanner EDA V13.0 has been used which reduces the power by 15%.
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