IJTEEE
International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289)
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IJTEEE >> Volume 2 - Issue 4, April 2014 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



Low Power Sram Design Using Multi-Bit Flip-Flop (MBFF)

[Full Text]

 

AUTHOR(S)

Lincy J, Sivasankar Rajamani P

 

KEYWORDS

Keywords: low power, clock power, merging, multi-bit flip-flop, time violation.

 

ABSTRACT

ABSTRACT: The increasing demand for battery-powered and green-compliant applications has made power management a dominant factor in SoC design. Clock power contributes 40% of total chip power.To get maximum reduction in power an algorithm has been proposed in which single-bit flip-flops are replaced with maximum possible Multi-Bit Flip-Flop (MBFF) without affecting the performance of the original circuit. Firstly mergable flip-flops are identified based on synchronous clocking and replaced without affecting the performance however replacement will change the location of flip-flops leading to timing and capacity constraint. Tanner EDA V13.0 has been used which reduces the power by 15%.

 

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