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International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289)
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IJTEEE >> Volume 2 - Issue 3, March 2014 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



High Performance Adder Circuit In Vlsi System

[Full Text]

 

AUTHOR(S)

Sentamilselvi M, Mahendran P

 

KEYWORDS

Keywords: Domino logic, Power, Delay, PMOS PUN, Integrated circuit.

 

ABSTRACT

ABSTRACT: In VLSI system. The integrated circuit design has important role. The various parameters are considering for design the circuit. The important parameters are power and delay. The different tools are used to perform the operation. However, here the combinational circuit (i.e. adder) designed by using different logic. The domino logic is the base of the proposed method. PMOS pull up network (PMOS PUN) is used to perform the operation. The proposed method includes the tradeoff of the power and delay. It designed by using tanner EDA Tool with 1V power supply and 0.5MHz frequency.

 

REFERENCES

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