Power Reduction In 5T SRAM Cell Using Circuit Level Approach In 45nm Technology
Deepti Kanoujia, Vishal Moyal
Keywords: 5T SRAM cell, CMOS (Complementary Metal Oxide Semiconductor), SRAM (Static Random Access Memory), Static Power Reduction.
ABSTRACT: This paper proposes CMOS 5T SRAM cell intended for the power reduction in it for advanced memory design. The aim is to reduce the static power dissipation. Various employed technologies are briefly described and discussed in the best possible way along with their strengths and weakness. The design metrics of a five transistor SRAM cell are discussed briefly and its performance is evaluated. Lastly, comparison between various methodologies is done to evaluate the best methodology to reduce power as per described technology. Performance and delay parameters will also be calculated using the tools, used in the entire project duration (H-spice). It is shown that the power in the new cell will be reduced up to 20% as compared to the conventional cell. As a trade-off, this may affect the area or speed of the cell, up to some extent. The entire work is done using tools like Microwind, DSCH and finally simulation done using H-Spice and thus power reduction. Delay is calculated using Cosmoscope. The technology used is 45nm technology.
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