IJTEEE

Open Access Journal of Scientific, Technology & Engineering Research


International Journal of Technology Enhancements and Emerging Engineering Research (ISSN 2347-4289)
QUICK LINKS
CURRENT PUBLICATIONS



IJTEEE >> Volume 3 - Issue 6, June 2015 Edition



International Journal of Technology Enhancements and Emerging Engineering Research  
International Journal of Technology Enhancements and Emerging Engineering Research

Website: http://www.ijteee.org

ISSN 2347-4289



Power Reduction In 5T SRAM Cell Using Circuit Level Approach In 45nm Technology

[Full Text]

 

AUTHOR(S)

Deepti Kanoujia, Vishal Moyal

 

KEYWORDS

Keywords: 5T SRAM cell, CMOS (Complementary Metal Oxide Semiconductor), SRAM (Static Random Access Memory), Static Power Reduction.

 

ABSTRACT

ABSTRACT: This paper proposes CMOS 5T SRAM cell intended for the power reduction in it for advanced memory design. The aim is to reduce the static power dissipation. Various employed technologies are briefly described and discussed in the best possible way along with their strengths and weakness. The design metrics of a five transistor SRAM cell are discussed briefly and its performance is evaluated. Lastly, comparison between various methodologies is done to evaluate the best methodology to reduce power as per described technology. Performance and delay parameters will also be calculated using the tools, used in the entire project duration (H-spice). It is shown that the power in the new cell will be reduced up to 20% as compared to the conventional cell. As a trade-off, this may affect the area or speed of the cell, up to some extent. The entire work is done using tools like Microwind, DSCH and finally simulation done using H-Spice and thus power reduction. Delay is calculated using Cosmoscope. The technology used is 45nm technology.

 

REFERENCES

[1] A.Veera Lakshmi and S.Priya, “Leakage Reduction and Stability Improvement Techniques of 10t Sram Cell: A Survey”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-3, Issue-7, December 2013.

[2] Adil Zaidi, Kapil Garg, Ankit Verma and Ashish Ra-heja, “Design & Simulation of CMOS Inverter at Nanoscale beyond 22nm”, International Journal of Emerging Science and Engineering (IJESE) ISSN: 2319–6378, Volume-1, Issue-5, March 2013.

[3] Ajay Gadhe and Ujwal Shirode , “Read stability and Write ability analysis of different SRAM cell structures”, International Journal of Engineering Research and Applications (IJERA), Vol. 3, Issue 1, January -February 2013, pp.1073-1078.

[4] Aminul Islam and Mohd. Hassan, “Variability Analysis of 6T and 7T SRAM Cell in Sub-45nm Technology”, IUM Engineering Journal, Vol. 12, No. 1, 2011.

[5] Anupriya Jain, “Analysis and Comparison of Leakage Reduction Techniques for 6T SRAM and 5TSRAM in 90nm Technology”, International Journal of Engineering Research & Technology (IJERT), Vol. 1 Issue 6, August – 2012, ISSN: 2278-018.

[6] Arash Azizi Mazreah, Mohammad Taghi Manzuri and Ali Mehrparvar , “A High Density and Low Power Cache Based on Novel SRAM Cell”, Journal of Computers, Vol. 4, NO. 7, July 2009.
[7] B.Yang and L. Kim. 2005. A low-power SRAM using hierarchical bit line and local sense amplifiers IEEE J. Soli State Circuits, vol. 40, no. 6, Jun. 2005, pp. 1366–1376.

[8] Chetna, Mr. Abhijeet, “Design of Low Power 5T-Dual Vth SRAM-Cell”, I OSR Journal of Engineering May. 2012, Vol. 2(5) pp: 1128-1132.

[9] Deepak Aggarwal, Praveen Kaushik, and Narender Gujran, “Comparative Study of 6T, 8T and 9T SRAM Cell”, International Journal of Latest Trends in Engi-neering and Technology (IJLTET), Vol. 1 Issue 2 July 2012, ISSN: 2278-621X

[10] G. Boopathi Raja and M. Madheswaran, “Design and Analysis of 5-T SRAM Cell in 32nm CMOS and CNTFET Technologies”, International Journal of Electronics and Electrical Engineering Vol. 1, No. 4, December, 2013.

[11] Jawar Singh, Dhiraj K. Pradhan, Simon Hollis and Saraju P. Mohanty, “ A single ended 6T SRAM Cell for ultra-low-voltage Applications”, IEICE Electronics Express, Vol.5, No.18, 750-755.

[12] Mamtha Samson and Satyam Mandavalli, “ Adiabatic 5T SRAM”, International symposiyum on Electronic System Design, (ISED): 267-272, Report No.: IIIR/TR/2011/-1.

[13] N.M. Sivamangai and K. Gunavathi, “A Low Power SRAM Cell with High ReadStability”, ECTI Transac-tions On Electrical Eng., Electronics and Communications Vol.9, NO.1 February 2011.

[14] S. Nalam and B. Calhoun, “Asymmetric sizing in a 45 nm 5T SRAM to improve read stability over 6T,” in Proc. 2009 IEEE Custom Integrated Circuits Conf. (CICC), 2009, pp. 709–712.

[15] Sapna Singh, Neha Arora and Prof. B.P. Singh, “Simulation and Analysis of SRAM Cell Structures at 90nm Technology”, International Journal of Modern Engineering Research (IJMER), Vol.1, Issue.2, pp-327-331 ISSN: 2249-6645.

[16] Shilpi Birla, Neeraj Kr. Shukla, Manisha Pattanaik and R.K.Singh, “Device and Circuit Design Challenges for Low Leakage SRAM for Ultra Low Power Applications”,Canadian Journal on Electrical & Electronics Engineering Vol. 1, No. 7, December 2010.

[17] Shyam Akashe, Sushil Bhushan and Sanjay Sharma, “High Density and Low Leakage Current Based 5T SRAM Cell Using 45 nm Technology”, Romanian Journal of information Science and Technology, Volume 15, Number 2, 2012, 155–168.

[18] Sushil Kumar Gupta and R.K. Chauhan, “Low- Power Analysis of Various 1-Bit SRAM Cells Using SPICE”, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE) Volume 2, Issue 8, August 2013, ISSN: 2278 – 909X.

[19] Vatsala S. Bannikatti and Asst. Prof. Rekha S, “De-sign of low power SRAM using 5T in Cadence tool”, International Journal of Ethics in Engineering & Man-agement Education, (ISSN: 2348-4748, Volume 1, Issue 4, April, 2014).